1. Field of the Invention
The present invention relates to a flip-flop circuit and a prescaler circuit including the same.
2. Description of Related Art
In recent years, miniaturization and reduction in weight of devices have been in progress in mobile communications terminals. Thus, higher integration and miniaturization of semiconductor integrated circuits that constitutes such devices are also required. A PLL circuit which is provided in the semiconductor integrated circuit is composed of source coupled logic (SCL) circuits with use of Bi-CMOS process technique. Thus, the PLL circuit is able to operate in high speed. However, from demands in the market described above, lower voltage, lower current consumption and higher speed in operation are required for the PLL circuit. Note that a prescaler circuit provided in the PLL circuit is a circuit that operates in high speed to control the operating frequency of the PLL circuit. Therefore, the prescaler circuit influences the current consumption of the PLL circuit.
FIG. 3 is a block diagram showing a prescaler circuit 200 for dividing the frequency of a clock signal by an integer 3 or 4 according to a related art. Hereinafter, a frequency division ratio is expressed as 1/n when divided by n (n is a natural number) by the prescaler circuit.
That is, FIG. 3 is a block diagram showing the prescaler circuit 200 for dividing the frequency of a clock signal with either of the frequency division ratios 1/3 and 1/4. Further, FIG. 4 is a circuit diagram showing a transistor configuration of a NOR circuit provided in a logic control circuit 2. Further, FIG. 5 is a circuit diagram showing a transistor configuration of a conventional flip-flop circuit provided in a flip-flop circuit group 1.
In the prescaler circuit 200 shown in FIG. 3, the flip-flop circuit group 1 is provided with a flip-flop circuit 100 and a flip-flop circuit 101 connected in cascade with each other. Further, the logic control circuit 2 is provided with a NOR circuit 102 and a NOR circuit 103. The high potential side power supply terminal of each of the flip-flop circuits 100 and 101 is connected to a power supply voltage terminal VDD. The low potential side power supply terminal of each of the flip-flop circuits 100 and 101 is connected to a ground voltage terminal GND. Note that, though not shown in FIG. 3, the high potential side power supply terminal of each of the NOR circuits 102 and 103 is connected to the power supply voltage terminal VDD. The low potential side power supply terminal of each of the NOR circuits 102 and 103 is connected to the ground voltage terminal GND.
Clock terminals Clock and Clock_b of the prescaler circuit 200 are connected to corresponding clock input terminals CK and CK_b of the flip-flop circuits 100 and 101. An output terminal Dout of the flip-flop circuit 100 is connected to an input terminal Din of the flip-flop circuit 101. An output terminal Dout_b of the flip-flop circuit 100 is connected to an input terminal Din_b of the flip-flop circuit 101 and an input terminal A of the NOR circuit 102. An output terminal Dout of the flip-flop circuit 101 is connected to an output terminal Dout of the prescaler circuit 200 and an input terminal B of the NOR circuit 103.
An output terminal Dout_b of the flip-flop circuit 101 is connected to an output terminal Dout_b of the prescaler circuit 200. An input terminal CTL of the prescaler circuit 200 is connected to an input terminal B of the NOR circuit 102. An output terminal Y of the NOR circuit 102 is connected to an input terminal A of the NOR circuit 103. An output terminal Y of the NOR circuit 103 is connected to an input terminal Din of the flip-flop circuit 100. An output terminal Y_b of the NOR circuit 103 is connected to an input terminal Din_b of the flip-flop circuit 100. Note that, for example, a signal named “Dout” and a signal named “Dout_b” (added “_b” to “Dout”) constitute a pair of differential signals. The other signals also constitute a pair of differential signals when expressed in the same fashion.
The output terminals Dout and Dout_b of the prescaler circuit 200 are connected to an external synchronous counter (not shown), for example. Counting bits of this counter is input to the input terminal CTL of the prescaler circuit 200 as a switching control signal for switching the frequency division ratio of the prescaler circuit 200. The logic control circuit 2 outputs a logic operation result obtained based on output data of the flip-flop circuit 100, output data of the flip-flop circuit 101, and the switching control signal as a feedback signal to the flip-flop circuit 100. Note that the frequency division ratio of the prescaler circuit 200 is switched as a result of the change of the logic operation result based on the switching control signal. Note that the configuration of the prescaler circuit as described above is disclosed in Japanese Unexamined Patent Application Publication No. 6-258465.
For example, when the switching control signal output from the synchronous counter (not shown) is H level, the prescaler circuit 200 indicates the frequency division ratio 1/4. In contrast, when the switching control signal output from the synchronous counter is L level, the prescaler circuit 200 indicates the frequency division ratio 1/3.
Referring next to FIG. 5, a circuit configuration and an operation of the flip-flop circuit of the related art will be described.
FIG. 5 is a circuit diagram showing a circuit configuration of a conventional flip-flop circuit formed by using Bi-CMOS technique. In the circuit shown in FIG. 5, transistors 5 to 8 are N-channel MOS transistors. Transistors 9 to 16 are NPN-type bipolar transistors. Note that the on-off state of each of the transistors 5 to 8 is controlled by a clock signal CK or a clock signal CK_b which is the inverted signal of the clock signal CK.
First, when the clock signal CK is H level and the clock signal CK_b is L level, an externally-supplied input signal is applied to the base of each of the transistors 9 and 10 through the corresponding input terminals Din and Din_b. Then, the externally-supplied input signal is amplified by a first differential circuit composed of resistors 17 and 18 and the transistors 9 and 10.
Next, when the clock signal CK changes from H level to L level and the clock signal CK_b changes from L level to H level, the signal amplified by the first differential circuit is held by a second differential circuit composed of the transistors 11 and 12. That is, the resistors 17 and 18, the transistors 5 and 6, and the transistors 9 to 12 constitute the master-side latch circuit in the conventional flip-flop circuit.
The signal amplified by the first differential circuit is held by the second differential circuit, and is applied to the base of each of the transistors 13 and 14 at the same time. Then, the amplified signal is further amplified by a third differential circuit composed of resistors 19 and 20 and the transistors 13 and 14. Then, the signal amplified by the third differential circuit is applied to each of the output terminals Dout and Dout_b as an output signal of the flip-flop circuit.
Next, when the clock signal CK changes from L level to H level and the clock signal CK_b changes from H level to L level, the signal amplified by the third differential circuit is held by a fourth differential circuit composed of the transistors 15 and 16, and the signal held by the forth differential circuit is applied to each of the output terminals Dout and Dout_b as the output signal of the flip-flop circuit. That is, the resistors 19 and 20, the transistors 7 and 8, and the transistors 13 to 16 constitute the slave-side latch circuit in the conventional flip-flop circuit. Note that the configuration of the flip-flop circuit as described above is disclosed in Japanese Unexamined Patent Application Publication No. 2005-303884.